1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing a semiconductor device.
2. Description of the Related Art
In semiconductor integrated circuits, in particular, integrated circuits including MOS transistors, the integration degree has been continuously increased. With this increase in the integration degree, the size of MOS transistors used in integrated circuits has been reduced to the order of nanometers. As reduction in the size of MOS transistors proceeds, leakage current is difficult to suppress. Accordingly, from the standpoint of providing a necessary current, reduction in circuit area is difficult to achieve, which has been problematic. In order to address such a problem, a surrounding gate transistor (hereafter referred to as an “SGT”) having the following configuration has been proposed: a source, a gate, and a drain are disposed in a direction perpendicular to a substrate, and a gate electrode is disposed so as to surround a pillar-shaped semiconductor layer (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
An existing inverter including SGTs has the following configuration: a single transistor is formed with respect to a single silicon pillar; accordingly, an nMOS transistor constituted by a single silicon pillar and a pMOS transistor constituted by a single silicon pillar are formed on a surface (for example, refer to Japanese Unexamined Patent Application Publication No. 2008-300558). In this configuration, since at least two silicon pillars are formed on a surface, an area corresponding to at least two silicon pillars is necessary.
An existing nonvolatile memory has a configuration in which a plurality of gates are formed with respect to a single silicon pillar (for example, refer to Japanese Unexamined Patent Application Publication No. 2014-57068). A gate insulating film is formed on the side wall of the silicon pillar. The silicon pillar is connected, at the upper end and the lower end, to a source line and a bit line.